"Our Analog and Custom Layout team has significant exposure in different domains for quality execution"
Implementation Methodologies
- Device Sizing
- Adjust transistor sizes to achieve optimized design.
- Logical effort is a gate delay model that takes transistor sizes into account
- Process and Mismatching Simulation
- Global deviations of model parameters
- Same change in all devices of the ASIC
- Worse-case corner analysis: (t)yp, (f)ast, (s)low
- Combined corners: process/voltage/temperature (PVT)
- Local deviations of model parameters
- Different change for each device of the ASIC
- Pelgrom Law
- Montecarlo statistical analysis
- The Art of Analog Layout General Matching Rules
- Unitary elements
- Large area devices
- Minimum distance
- Same orientation
- Same surrounding
- Same symmetry
- Common Centroid Arrays, PCell-Based Layout, Decoupling Guidelines
- Physical Verification
- Geometrical Rules
- Design Rule Checker
- Parasitics Extraction
- Motivation
- Extraction Tools
- DFM Techniques
- Dummy filling
- Antenna reduction
- Metal slotting
- Multiple contacts
- Extra guard rings
